FIG. 1 shows an example of a conventional information processing apparatus mounted with multiple general purpose or application specific processors. FIG. 1 shows an example of an application processor to be mounted on a mobile phone or on a personal digital assistant.
As shown in FIG. 1, information processing apparatus 301 has multiple information processing units and multiple shared resources commonly used by the respective information processing units, all of which are configured to be connected so that they can mutually send and receive information via internal bus 312.
In the case of the application processor shown in FIG. 1, the information processing unit is a general purpose processor such as CPU 302 or DSP 303, or a peripheral controller such as DMA controller (DMAC) 304, camera controller 305 or LCD controller 306.
Moreover, the shared resource is SDRAM controller 307 for controlling reading/writing of data with respect to SRAM 308 which is an internal memory and a SDRAM (Synchronous Dynamic Random Access Memory) which is an external memory, external bus bridge 309 which is an interface with an external bus to which the external memory (for example, flash memory) is connected, various peripheral devices 310 and 311, and the like.
In the information processing apparatus provided with such multiple information processing units, a common method is to use a standard bus as internal bus 312 and accordingly to design a bus interface of each information processing unit, in order to facilitate apparatus design or performance verification. As the standard bus, for example, AHB (Advanced High-performance Bus) for realizing AMBA (Advanced Microcontroller Bus Architecture) proposed by ARM Ltd. (Cambridge, England) has been known. It should be noted that the AHB has been described in detail, for example, in U.S. Pat. No. 5,740,461.